P-Bandwidth Priority Queues on Reconfigurable Tree of Meshes

the same subbus. Efficient parallel algorithms that use reconfigurable networks have been devised for many problems, such as sorting [3, 6, 8, 10, 16], matrix multiplication [12], finding the connected components of a graph [9] and image processing [7, 9]. Most such algorithms achieve an O(1) time complexity by considering the so called unit-time delay model, in which it is assumed that each broadcast takes constant time to reach all the processors in a subbus, regardless of its length (i.e., number of edges). However, the log-time delay model, where each broadcast takes a time which is logarithmic in the length of the subbus, is also considered. Since the implications of the subbus lengths for the actual performance of the network cannot be ignored, it is of paramount importance to find algorithms which reduce the maximum subbus length as much as possible. This paper presents a parallel implementation of a Pbandwidth priority queue, which is capable of storing at most nP keys. A priority queue with bandwidth P is a generalization of a classical priority queue, in which the usual operations of the data structure handle a set of P keys instead of only one key (e.g., see [13]). Specifically, the MIN operation returns the P smallest keys in the queue, the DELETEMIN operation removes such keys, while the INSERT(X) one adds P new keys into the queue, namely, those belonging to the set X. Therefore, when P 5 1 the usual priority queue results. The proposed implementation is based on a reconfigurable tree of meshes architecture of O(nP2) processors, and assumes that each switch has four I/O ports. The network has an O(P log n) maximum subbus length, and the computational times required by the priority queue operations are O(1) for all the operations, using the unit-time delay model, while they are O(1) for MIN and O(log P 1 log log n) for both DELETEMIN and INSERT(X), using the log-time delay model. For the latter model, the computational times are as good as the best times known for the EREW PRAM model ([13, 17]). The proposed network can be laid out in a classical Hshaped manner to occupy O(nP2) area in the VLSI model. In particular, when P 5 O(1), an optimal O(n) area results, since any priority queue storing O(n) keys has an obvious V(n) lower bound on the area. Moreover, when P 5 O(1) and the unit-time delay model is used, an optimal O(n) AT 2 also results. Although several VLSI implementations JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 40, 248–255 (1997) ARTICLE NO. PC961259